PhD in SW safety - industrial collaboration with KTH

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Today, safety electronic control require big and massive electronics which do not allow for small IoT highly distributed devices. Also, any new design require a very complex process of safety certification.

With this project we look for novel approaches to miniaturized safety control within System-On-Chips.

The objective of the project is to create a Verification & Validation framework which improves the paradigms used for high safety product development.

Specifically, it will focus on fault-injection to safety System-on-Chip/FPGA based platforms with the aim of modelling, error detection and self-healing.

In order to create tangible results, one or more prototypes of these platform will be developed and multiple approaches and techniques, as described in the project, will be implemented, tested and evaluated.

Additionally, other aspects, like intentional fault-injection (i.e. cybersecurity) will be considered.

The aim is to further implement these techniques on new products with target of massively reducing footprint (against the big complex PCBA designs) and enable safety-platforms on small wirelessly (e.g. 5G) control platforms.

The current state-of-the-art does not allow this per-se on SIL-4 safety systems but the developments on the VALU3S projects are expected to pave the way for it alongside other work. 

The preliminary activities during the project (which can be slightly changed, depending on the interest/profile of candidates) can be summarized in the following 2 bullet points:

  • How to detect and safely handle random and systematic errors on a single FPGA-SoC based design?
  • Given certified platforms, how do we minimize the effort of certification when adding functionalities? E.g. is it possible to move the safety function between certified platforms without re-validating?

 

Keywords: 

Functional safety analysis

A methodology for analysis of how fault propagate from subsystems to higher levels (the whole systems and beyond).

Fault-injection, soft-error mitigation, formal verification

Fault-injection on FPGAs

Fault and attack modelling.

Model-based mutation testing for fault injection

Reduce HW needed for V&V

Simplify SW modules reusability on a minimized platform

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Liljeholmen

Rosterigränd 4
117 61 Stockholm Vägbeskrivning Se sida

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